IC substrate in-plane coefficient of thermal expansion (CTE) testing measures the dimensional stability of package substrates in the X and Y directions across thermal cycling conditions, which is critical for semiconductor packaging reliability. Accurate CTE data enables engineers to minimize solder joint fatigue, warpage, and delamination caused by thermomechanical mismatch between the silicon die, substrate, and motherboard. This article covers the test principles, sample requirements, methods such as TMA and dilatometry, industry standards, and practical applications of in-plane CTE measurement for IC substrates.
Technical Overview
IC substrates function as the structural and electrical bridge between the silicon die and the printed circuit board in virtually all advanced semiconductor packages, including BGA, FCCSP, FCBGA, and SiP formats. Because these packages experience repeated thermal excursions during reflow soldering, burn-in, and field operation, the in-plane coefficient of thermal expansion (CTE) of the substrate directly governs thermomechanical stress at the bump, solder ball, and die-attach interfaces.
The in-plane CTE, denoted as alpha-x and alpha-y, describes the fractional length change of the substrate per degree of temperature change, expressed in ppm/degree Celsius. A typical silicon die expands at approximately 2.6 ppm/degree Celsius, while standard PCB materials expand at 14 to 18 ppm/degree Celsius. IC substrates are therefore engineered to an intermediate in-plane CTE, typically 8 to 17 ppm/degree Celsius below the glass transition temperature, in order to balance stress on the die side and the board side. Excessive CTE mismatch accelerates solder joint fatigue, induces package warpage, and can trigger interfacial delamination between the core, build-up dielectric layers, and copper circuitry.
In-plane CTE testing is performed in accordance with recognized standards such as ASTM E831, ISO 11359-2, IPC-TM-650, and JEDEC guidelines, providing material suppliers, substrate fabricators, and packaging houses with reproducible data for material qualification, finite element simulation, and reliability assessment.
Testing Samples
Core Materials and Copper-Clad Laminates
Bare substrate cores such as bismaleimide triazine (BT) resin systems, epoxy-glass laminates, low-Dk glass-fabric reinforced cores, and high-frequency substrate materials are tested either as supplied laminates or after copper etching. Copper foil is typically removed or etched away before measurement so that the reported CTE reflects the dielectric composite rather than the copper-constrained laminate.
Build-up Dielectric Films
Photosensitive build-up films and non-photosensitive dielectric coatings used in sequential build-up (SBU) processes are characterized as free-standing films or laminated on carrier cores, depending on the material form and the applicable specification.
Finished IC Substrates
Completed package substrates, including flip-chip ball grid array substrates, chip-scale package substrates, and embedded-die or 2.5D interposer structures, may be tested in panel form or as singulated units to verify that lamination, curing, and patterning processes have not shifted the CTE beyond the design window.
Sample Preparation Requirements
- Specimens are cut as flat strips or rectangular coupons, typically 6 to 10 mm in length for TMA testing, with parallel faces and burr-free edges.
- X-direction and Y-direction coupons are prepared separately, since glass-fabric weave asymmetry can produce anisotropic expansion.
- Moisture conditioning is controlled by pre-baking (for example, 105 degrees Celsius for 1 to 2 hours) followed by cooling in a desiccator, because absorbed moisture suppresses the measured CTE and shifts the apparent glass transition temperature.
- Sample thickness is measured at multiple points to support accurate dimensional normalization.
Testing Items
A comprehensive in-plane CTE evaluation for IC substrate materials typically includes the following measured parameters:
- In-plane CTE below the glass transition temperature (alpha-1, typically 30 to 260 degrees Celsius or 50 to 150 degrees Celsius depending on specification).
- In-plane CTE above the glass transition temperature (alpha-2), which characterizes the softened rubbery regime.
- Glass transition temperature (Tg) determined from the expansion curve inflection.
- Z-axis (out-of-plane) CTE for through-hole and via reliability correlation, often measured simultaneously or in a companion test.
- Cure-dependent and lot-to-lot CTE variation for statistical process control purposes.
Testing Methods
Thermomechanical Analysis (TMA)
TMA is the most widely used method for IC substrate CTE measurement, performed per ASTM E831, ISO 11359-2, and IPC-TM-650 procedures. The specimen is placed on a quartz platform and contacted by a low-force quartz expansion probe. The furnace ramps at a controlled heating rate, commonly 3 to 5 degrees Celsius per minute, across a programmed temperature range such as -50 to 300 degrees Celsius or 30 to 260 degrees Celsius. The instrument records dimensional change versus temperature, and the CTE is calculated from the slope of the expansion curve over the specified interval using the relationship alpha equals delta-L divided by (L-zero multiplied by delta-T).
Push-Rod Dilatometry
Dilatometry per ASTM E228 provides high-precision bulk expansion measurement over larger specimens and wider temperature ranges. It is particularly valuable for core laminate qualification where measurement uncertainty must be minimized.
Strain Gauge Method
High-temperature foil strain gauges bonded to the substrate surface allow in-plane CTE determination by measuring thermal strain relative to a reference material of known expansion. This approach is useful for full-thickness finished substrates and for verifying TMA results.
Optical Non-Contact Methods
Digital image correlation, laser extensometry, and moire interferometry enable full-field, non-contact measurement of in-plane expansion. These techniques can map local CTE variations around copper-dense regions, via arrays, and warpage-sensitive zones that traditional contact methods cannot resolve.
Data Reduction and Reporting
- Expansion curves are segmented into pre-Tg and post-Tg regions, with linear regression applied to each segment.
- Reported results include alpha-1, alpha-2, Tg onset and midpoint, specimen orientation, conditioning history, and the specific temperature intervals used.
- Anisotropy between machine and transverse directions is documented because it influences warpage simulation accuracy.
Applications
- Material qualification and incoming inspection for core laminates, build-up films, and finished substrates at packaging factories.
- Finite element analysis and warpage modeling inputs for package design, reflow profile optimization, and assembly yield improvement.
- Reliability engineering for temperature cycling, thermal shock, and high-temperature storage qualification programs.
- Research and development of advanced substrates, including glass-core substrates, low-CTE laminates, and materials for 2.5D and 3D heterogeneous integration.
- Process control for lamination, post-etch, and curing parameters that influence the degree of cure and residual stress state.
- Vendor comparison and supply chain specification alignment between substrate makers, OSATs, and IDM reliability teams.
FAQ
What is a typical in-plane CTE specification for IC substrates?
Conventional rigid substrates based on BT or epoxy-glass cores generally target 10 to 17 ppm/degree Celsius below Tg, while high-end flip-chip and 2.5D interposer substrates are engineered toward 6 to 10 ppm/degree Celsius to closely match silicon and reduce die stress.
Why is in-plane CTE more critical than out-of-plane CTE?
In-plane CTE mismatch drives solder joint shear strain and package warpage, which are the dominant failure accelerators in area-array packages. Out-of-plane CTE remains important for via and through-hole reliability but has less influence on bump-level stress.
What temperature range should be used for testing?
The range must cover the intended service and assembly conditions. Common windows include 30 to 260 degrees Celsius to bracket lead-free reflow, and segmented reporting below and above Tg. The chosen interval must always be stated with the result.
How does moisture affect CTE test results?
Absorbed moisture plasticizes the resin, lowering the apparent Tg and altering the measured expansion slope. Standard practice requires pre-baking and desiccator cooling prior to testing to ensure reproducibility.
How are TMA results made traceable and repeatable?
Laboratories calibrate TMA instruments with certified reference materials such as aluminum and fused silica, verify force and furnace ramp accuracy, replicate specimens in both orientations, and report full test conditions per ASTM E831 and ISO 11359-2 requirements.
Can finished multilayer substrates be tested directly?
Yes. Finished substrates can be measured as coupons, but the effective CTE reflects the copper distribution and layer stack. Design intent should specify whether the acceptance limit applies to the raw laminate, the core, or the completed stack-up.
